Capacitors are elements that are used extensively in semiconductor devices for storing an electrical charge. Capacitors essentially comprise two conductive plates separated by an insulator. The capacitance, or amount of charge held by the capacitor per applied voltage, depends on a number of parameters such as the area of the plates, the distance between the plates, and the dielectric constant value for the insulator between the plates, as examples. Capacitors are used in filters, analog-to-digital converters, memory devices, control applications, and many other types of semiconductor devices.
One type of capacitor is a MIM capacitor, which is frequently used in mixed signal devices and logic devices, as examples. MIM capacitors are used to store a charge in a variety of semiconductor devices. MIM capacitors are often used as a storage node in a memory device, for example. A MIM capacitor is typically formed horizontally on a semiconductor wafer, with two metal plates sandwiching a dielectric layer parallel to the wafer surface. Often, one of the metal plates is formed in a metallization layer or metal interconnect layer of a semiconductor device.
A prior art semiconductor device 100 is shown in FIG. 1. The semiconductor device 100 includes a substrate 104 having a dynamic random access memory (DRAM) region and a logic region. A plurality of transistors 106 are formed in and over the substrate 104, wherein transistors 106 in the DRAM region comprise access transistors of the DRAM devices. A plurality of MIM capacitors 102 are formed in a second insulating layer 116 which comprises a single interconnect layer of the device 100, as shown. The MIM capacitors 102 comprise a bottom plate electrode 118, a dielectric layer 120 and a top plate electrode 122. The MIM capacitors 102 make electrical contact to underlying bitlines 108 by contacts 112 that are formed in a first insulating layer 110. A stop layer 114 may be disposed between the first insulating layer 110 and the second insulating layer 116. In the logic region, contacts 126 are formed to provide electrical contact to component regions and gates of transistors, as examples.
It is challenging to merge the manufacturing of capacitors 102 in DRAM regions with logic circuits in the logic region. For example, the topography created by the MIM capacitor 102 requires the use of a thick insulating layer 124 to successfully cover the MIM capacitor topography. The thick insulating layer 124 creates a higher aspect ratio for the electrical contacts 126 in the logic region. The aspect ratio of the contacts may be 10:1 to 25:1, as examples. These high aspect ratio contacts 126 are problematic because the contact pattern is difficult to etch through the thicknesses of the dielectric layers 124, 116, 114 and 110, and also because it is difficult to fill the narrow, deep contact patterns with a conductive material.
Another problem with the prior art MIM capacitor 102 structure shown in FIG. 1 is that there is often an insufficient overlap margin d1 between the top plate electrode and the bitline contact 128. The margin d1 may comprise 0.2 to 0.3 μm, as an example. This can lead to shorts, resulting in device failures.